Logic Synthesis and Verification Algorithms
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Logic Synthesis and Verification Algorithms
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Amazon Business : For business-only pricing, quantity discounts and FREE Shipping. Register a free business account Paperback: 596 pages Publisher: Springer; 1996 edition (February 10, 2006) Language: English ISBN-10: 0387310045 ISBN-13: 978-0387310046 Product Dimensions: 6.1 x 1.4 x 9.2 inches Shipping Weight: 2.3 pounds (View shipping rates and policies)
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Book Description
This book blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.
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