vhdl

Edit useful +1 vhdl VHDL full name of Very-High-Speed ​​Integrated Circuit HardwareDescription Language, was born in 1982. End of 1987, VHDL and the U.S. Department of Defense confirmed by the IEEE standard hardware description language. Since the IEEE-1076 (referred 87 version), each of the EDA companies have launched their VHDL design environment, or declare their own design tools and VHDL interface. 1993,Moncler, IEEE for VHDL was revised from a higher level of abstraction and system capacity expansion VHDL description of the content, announced a new version of VHDL, the IEEE 1076-1993 standard version, referred to as 93 edition. VHDL and Verilog as IEEE industry standard hardware description language, supported by many EDA companies in the field of electronic engineering, has become the de facto universal hardware description language. Table of Contents

1 Introduction

2 Features

2.1 is powerful,R4i 3DS, flexible design 2.2 supports a wide, easy to modify

3 advantage

4 simple case

1 Introduction VHDL language is a high-level language for circuit design. It appeared in the late 1980s. Was originally developed by the U.S. Department of Defense for the U.S. military to improve design reliability and reduce the development cycle using a smaller range of design language. VHDL translated into Chinese is ultra high speed integrated circuit hardware description language, mainly used in digital circuit design. Currently, it is in China's applications are used mostly in the FPGA / CPLD / EPLD design. Of course, the strength of relatively strong in some units, it has also been used to design ASIC. VHDL mainly used to describe the structure of digital systems, behavior, functionality and interfaces. In addition to containing many statements outside with hardware features, VHDL language of form, style and syntax description is quite similar to the general high-level computer language. Structural features of VHDL program is an engineering design, or design entity (can be a component of a circuit module or a system) into external (or called visible part, and ports) and internal (also known as non-visible part) both entities involved in the completion of the internal functions and algorithms section. In response to a design entity defines the external interface, once its internal development is complete, the other designs you can directly call this entity. This entity is divided into inner and outer part of the design concept is the basic point of VHDL system design. 2 Features Compared with other hardware description language, VHDL has the following features: a powerful,R4 3DS, flexible design with a powerful VHDL language constructs, you can use the source code to a clear and concise description of complex control logic. It has a multi-level design description features, layers of refinement, the final circuit level can be directly generated description. VHDL supports synchronous circuits,Veste Moncler, asynchronous circuits and random circuit design, which is the other hardware description language can not be compared. VHDL also supports a variety of design methods, supports both bottom-up design, and support top-down design; supports both modular design, but also supports hierarchical design. Supports a wide, easy to modify the VHDL IEEE standard has become a standard hardware description language, most EDA tools support almost all VHDL, VHDL which is widely used in the further promotion and laid the foundation. In the hardware circuit design process,R4i 3DS, the main design document is written in VHDL source code, because VHDL readable and structured, so easy to modify the design. Powerful system capable VHDL hardware description has a multi-level design description function, which can describe the system-level circuit, and can describe the gate-level circuits. The description can be used both behavioral descriptions, register transfer description or schema, you can use three mixed mixed-level description. Further, VHDL supports inertial delay and transmission delay, can accurately establish the hardware circuit model. VHDL supports predefined and custom data types, to bring greater freedom hardware description, enables designers to easily create high-level system models. Device-independent design,Monster Beats by dre Pro, independent designers and process design using VHDL, you do not first consider the choice to complete the design of the device, you can concentrate on design optimization. When the design description is complete, you can use a variety of device structure to achieve its function. Strong portability is a standardized VHDL hardware description language, with a design description can be supported by different tools, making it possible to design descriptions transplant. Easy sharing and reuse of VHDL-based library (Library) design method, you can create a variety of modules that can be used again. These modules can be pre-designed or used in previous designs archive module, these modules will be stored in the library, the design can be carried out at a later reuse, you can make design results in the design of communication and sharing among staff, reduce hardware circuit Design. Three advantages (1) and compared to other hardware description language, VHDL behavioral description has a stronger ability to determine the optimal system design he became a hardware description language. Strong ability to describe the behavior of a specific device structure is to avoid, from a logical description of the behavior and design of large-scale electronic systems important guarantee. (2) VHDL rich simulation statements and library functions, making any large system design in the early function of the system will be able to examine the feasibility of the design, ready for design simulation. (3) VHDL behavioral description statements capabilities and structure of the program that he has decided to support the design of large-scale decomposition and re-use of existing designs feature. Large-scale systems to meet market demand efficient, high-speed finish must have even more people together on behalf of groups working in parallel to achieve. (4) For the completion of a determined using VHDL design, you can use EDA tools for logic synthesis and optimization, and automatically VHDL description of the design into a gate-level netlist. (5) VHDL description of the design has a relative independence, the designer can not understand the structure of hardware, do not manage to achieve the final design of what the target device, and independent design. 4 Simple Example --- VHDL Example library ieee; use ieee.std_logic_1164.all; - library declaration entity TONE is port (A, B: in std_logic; - entities defined C: out std_logic); end TONE; architecture EX of TONE is - defined structure begin C <= A OR B; end EX; VHDL is not case sensitive