A device for transferring data arrays between at least two buses, the device comprising storage means for storing at least one data array, a first input/output interface for transferring data arrays in a first direction from a first of the buses (RBUS) to the storage means and in a second direction from the storage means to the first bus (RBUS), a second input/output interface for transferring.
One of the layers of the protocol stack of the ETSI HIPERLAN or IEEE 802.11 series protocols is the Medium Access Control layer, usually called MAC layer. MAC layer operations require access to both protocol data and payload data.
Because of the high data rates, the MAC layer must have a short response time in order to handle all of the tasks in a timely fashion. This short response time cannot be obtained using common state-of-the-art software implementation techniques. Hence, a dedicated hardware implementation would be required according to the state of the art.
However, this would result in an expensive and inflexible design occupying a large silicon area. An example of a known device for transferring data arrays, which is commonly used in high-speed data transmission systems, is a Direct Memory Access device (DMA). 
Such a DMA is connectable between a first and a second bus and capable of quickly transferring data from the first to the second bus and vice versa. However, in order to decide the direction of the data transfer, a plurality of initial programming steps is required for setting up the DMA before data transfer from one bus to the other can be started. As a result, a DMA does not enable one to quickly switch the direction of data transfer. A device for transferring data arrays between buses is known from U.S.
5,802,054 to Bellenger. The device includes storage means for storing at least two data arrays, a first input/output interface for transferring data arrays in a first direction from a first of the buses to the storage means and in a second direction from the storage means to the first bus, a second input/output interface for transferring second data arrays different from the first data arrays in a third direction from a second of the buses to the storage means and in a fourth direction from the storage means to the second bus. The first interface is provided with first selecting means for selecting one of said first and second directions and the second interface is provided with second selecting means for selecting one of said third and fourth directions. In this device, the inputting of a first data array via the first interface to the storage means requires two clock cycles, since the data has to pass via an internal bus.
Then, if a second data array has to be inputted to the storage means using the second interface, two more consecutive clock cycles have to be counted, since the second data array has to pass via the same internal bus, the arbiter and the memory bus. So the inputting of two different data arrays into the storage means requires four clock cycles. As result, in order to change the direction of data transfer, multiple clock cycles are needed.