Our first formal lab proposal assignment is suggestion of digital design.
In this assignment, 3 types of main IC (LSI) devices are compared, and the best design for the writer will be shown.
The 3 types are 74 Logic (HC, LS or TTL compatible logic IC), CPLD, or FPGA.
Here is the VHDL source code:
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library IEEE;
use IEEE.std_logic_1164.all;
entity seven_seg is
port (din : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(7 downto 0) );
end seven_seg;
architecture seven_seg_body of seven_seg is
begin
process(din)
begin
if din = "0000" then dout <= "11111100";
elsif din = "0001" then dout <= "01100000";
elsif din = "0010" then dout <= "11011010";
elsif din = "0011" then dout <= "11110010";
elsif din = "0100" then dout <= "01100110";
elsif din = "0101" then dout <= "10110110";
elsif din = "0110" then dout <= "10111110";
elsif din = "0111" then dout <= "11100000";
elsif din = "1000" then dout <= "11111110";
elsif din = "1001" then dout <= "11110110";
elsif din = "1010" then dout <= "11101110";
elsif din = "1011" then dout <= "00111110";
elsif din = "1100" then dout <= "10011100";
elsif din = "1101" then dout <= "01111010";
elsif din = "1110" then dout <= "10011110";
elsif din = "1111" then dout <= "10001110";
else dout <= "00000000";
end if;
end process;
end seven_seg_body;
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It's supposed to display like below.

7セグメント表示の2進数(16進数)デコーダのVHDLサンプルコード。
4つのInputスイッチの入力状態から0~Fを7セグメントLED(アノードコモンタイプ)に表示させます。

全員命に別状はなく、すぐに退院できるようです。ヴァージニアテックのような大惨事に至ることはなかったですが、やはりアメリカは危険がいっぱいなんだなと思いました。