1. Background template only for the JVM interpreter: How opcode and addressing mode based on the bytecode generated assembly code. Byte-code and assembler code example used herein, see the Bowen: pass by value or by reference? 2. This article does not go into addressing modes expand elaborate addressing modes, we focus on the IA32-64 Intel architecture instruction formats: Under brief description, more intel manuals refer to: - Prefixes: Pertaining opcode Opcode , given its lock, repeat and other semantic .- REX Prefix: - Specify GPRs and SSE registers .-- Specify 64-bit operand size .-- Specify extended control registers.-Opcode: opcodes, such as mov, push.- Mod R / M: addressing relevant, specific see manual. -SIB: And Mod R / M combine specific addressing. -Displacement: With Mod R / M and SIB specific addressing. -Immediate: Immediate. For Mens Nike Free 3.0 Wool Skin Shoes Blue Yellow the above Opcode, Mod R / W, SIB, disp, imm if not understand, there is a concept compilation Sentence:% mov% eax,% rax, -0x18 (% rcx,% rbx, 4) if the phrase compilation also do not understand, then with the following: - Base + (Index * Scale) + Displacement - Using all the addressing Air Max 2011 Womens Grey Green Black components together allows efficientindexing of a two-dimensional array when the elements of the array are 2, 4, or 8 bytes in size .3 legitimate value (64) Follow these four parameters under legal argument: o Displacement - An 8-bit, 16-bit, or 32-bit value.o Base - The value in a 64-bit general -purpose register.o Index - The value in a 64-bit general-purpose register.o Scale factor - A value of 2, 4, or 8 that is multiplied by the index value.4, Mod R / M (32 位 hunt address) we will use later Mod R / M byte, so the 32-bit addressing format posted here: Remarks on the table, the first one will be used in our example, so pay attention here Under: The [-] [-] nomenclature means a SIB follows Nike Free TR Fit the ModR / M byte.The disp32 nomenclature denotes a 32-bit displacement that follows the ModR / M byte (or the SIB byte if one is present) and that isadded to the index.The disp8 nomenclature denotes an 8-bit5, SIB (32-bit addressing) Also, 2015 Nike Free 5.0 since use of the Mod R / M byte, then the SIB byte is also possible to use: 6, Example 6.1, ready to work look at an actual example. The following code is generated mov assembly code: void Assembler :: movl (Address dst, Register 535807 103 Jordan CP3.VI White Black Game Royal Sport Red CP3 Shoes 2013 Sale src) {InstructionMark im (this); prefix (dst, src); emit_int8 ((unsigned char) 0x89); emit_operand (src, dst) ;} prefix (dst, src) is to deal with prefix and REX prefix, here we are not concerned. emit_int8 ((unsigned char) 0x89) as the name suggests is to generate a byte, that byte content 0 × 89 represent? First in no hurry, there are Nike Air Max a emit_operand (src, dst), which is a long code, we probably look: void Assembler :: emit_operand (Register reg, Register base, Register index, Address :: ScaleFactor scale, int disp , RelocationHolder const \u0026 amp; rspec, int rip_relative_correction) {relocInfo :: relocType rtype = (relocInfo :: relocType) rspec.type (); // Encode the registers as needed in the fields they are used in int regenc = encode (reg) \u0026 lt ; \u0026 lt; 3; int indexenc = index- \u0026 gt; is_valid () encode (index) \u0026 lt; \u0026 lt; 3:? Nike Air Zoom Flight The Glove 0; int baseenc = base- \u0026 gt; is_valid () encode (base):? 0; if (base- \u0026 gt; is_valid ()) {if (index- \u0026 gt; is_valid ()!) {assert (scale = Address :: no_scale, \u0026 quot; inconsistent address \u0026 quot;); // Nike Air Max 2015 Men [base + index * scale + disp] if (disp = = 0 \u0026 amp; \u0026 amp; rtype == relocInfo :: none \u0026 amp; \u0026 amp; base = rbp LP64_ONLY! (\u0026 amp; \u0026 amp;! base = r13)) {// [base + index * scale] // [00 reg 100] [ss index base] / *************************** key points: Focus here ************ ************** / assert (! index = rsp, \u0026 quot; illegal addressing mode \u0026 Nike Air Max 2015 Men quot;); emit_int8 (0x04 | regenc); emit_int8 (scale \u0026 lt; \u0026 lt; 6 | indexenc | baseenc) ;} else if (is8bit (disp) \u0026 amp; \u0026 amp; Mens Nike Free Run 3 Shoes Black Red 3 rtype == relocInfo :: none) {// ...} else {// [base + index * scale + disp32] // [10 reg 100] [ss index base] disp32 assert (! index = rsp, \u0026 quot; illegal addressing mode \u0026 quot;); emit_int8 (0x84 | regenc); emit_int8 (scale \u0026 lt; \u0026 lt; 6 | indexenc | baseenc); emit_data (disp, rspec, disp32_operand);} } else if (base == rsp LP64_ONLY (|| base == r12)) {// ...} else {// ...}} else {// ...}} The above code concerns have been mark, where we pull it out, and before Mens Nike Free 3.0 Wool Skin Shoes Blue Yellow the text of the emit_int8 ((unsigned char) 0x89) combined: emit_int8 ((unsigned char) 0x89) emit_int8 (0x04 | regenc); emit_int8 (scale \u0026 lt; \u0026 lt; 6 | indexenc | baseenc); finally it generates the following assembly code (64 Nike Air Zoom Flight The Glove machines): mov% eax, (% rcx,% rbx, 1) Well, the question arises: how come compilation sentence Nike Air Max 2015 Women above? 6.2 The calculation process we give the following values: regenc = 0x0, scale \u0026 lt; \u0026 lt; 6 | indexenc | baseenc = 25 for simple operation can be obtained: emit_int8 ((unsigned char) 0x89) // get 0x89emit_int8 (0x04 | regenc); // get 0x04emit_int8 (scale \u0026 lt; \u0026 lt; 6 | indexenc | baseenc); // get together is three bytes 0x19: 0x89 0x04 0x191,0 Air Jordan Outlet × 89 corresponds to what? As can be seen from the table because JVM work at 64 under, so it is necessary to coordinate REX.W 'preliminary,' but in our case, it happens to be zero. Mainly to see the 89 / r: MOV r / m64, r64 // 64 bit value to Air Max 2011 Womens Blue Black the register to register or memory address what 2,0 × 04 represent? Now we have to use the above Mod R / M and SIB table the table. With the second byte 0 × 04 check Mod R / M table, we can see the source operand is a register EAX, while addressing type is known [-] [-] type, meaning: The [-] [- -] nomenclature means a SIB follows the ModR / M byte.3,0 × 19 represent? Continue to check SIB table, the corresponding byte 0 × 19 are: base = ECXscaled index = EBX4, assembly code: // 32 mov% eax,% (ecx, ebx, 1) // 64 位 mov% rax,% ( rcx, rbx, 1) 7, Conclusion This article briefly discusses: How opcode and addressing mode according to the bytecode generated assembly code. End.JVM template interpreter: how to generate assembly code to byte code?